In a semiconductor memory device, the data stored in memory cells may be incidentally destroyed by alpha rays, noise, or the like. This type of data destruction occurs more often when the amplitude of the data stored in the memory cells (i.e., the difference between the voltage of H level and L level) is decreased. Therefore, the influence of such data destruction is more important now that low voltage semiconductor memory devices are in greater demand.
Accordingly, Japanese Patent Laid-open Application Showa 58-169958 discloses a device in which the amplitude of the data in memory cells is widened as much as possible within the limit of a given power voltage. This conventional device will now be described with reference to FIGS. 1 and 2. FIG. 1 shows a step-up circuit for a conventional static RAM. As shown, a memory cell 10 is composed of four N-channel MOSFETs ("NMOS transistors") T20-T23 and two high resistance loads R1 and R2. Multiple memory cells 10 are arranged in matrix form and each memory cell 10 is connected to a word line WL and a pair of bit lines BL and /BL (a bar of BL). Each word line WL is long enough to be connected to 256 memory cells, and there are 512 word lines, for example. The pair of bit lines BL and /BL are used to write data in or read data out of the memory cells 10, and there are 1024 pairs of bit lines BL and /BL, for example.
Data buses DB and /DB are coupled to the pair of bit lines by means of a column gate 12, which is composed of four transistors T14-T17 controlled by row selective signals Y and /Y. Bit line load transistors T18 and T19 are connected between a power source (not shown) and the bit lines BL and /BL, respectively. A write-in circuit 14 is composed of two P-channel MOSFETs ("PMOS transistors") and two NMOS transistors T10-T13. An inverter composed of PMOS transistor T8 and NMOS transistor T9 functions as a word line driver 16, and there are as many word line drivers as the number of word lines WL. The word line driver 16 is driven by the output of a row selective decoder 18.
Further, a step-up control circuit 20 is composed of three PMOS transistors T1, T3, and T4, three NMOS transistors T2, T5, and T6, and a delay circuit 22. Additionally, a step-up circuit 24 is composed of a step-up capacitor C1 and a PMOS transistor T7.
Next, the operation of the conventional device will be described with reference to the timing chart of FIG. 2. In the device of FIG. 1, when data is written in the memory cell 10, the write-in signals IN and /IN are illustratively input to the write-in circuit 14, which is composed of four transistors T10-T14, so that the write-in signals IN and /IN go to logic L and H, respectively, at a time when the write enable signal /WE is set to a low level. In this case, the data bus /DB is raised up to the voltage of power source line Vdd when the write enable signal goes to logic L, as shown in FIG. 2. Further, the bit line /BL is also raised up to nearly Vdd, because the PMOS transistors and NMOS transistors that form the column gate 12 are connected in parallel and the bit line load transistor is a PMOS transistor.
Additionally, the write enable signal /WE is input to the step-up control circuit 20 and inverted to the write enable signal WE by means of transistors T1 and T2, which form an inverter. The write enable signal WE is supplied to the gates of the transistors T4 and T5. The write enable signal /WE is also delayed by the delay circuit 22 for a predetermined period to form the signal /WEd, which is supplied to the gates of transistors T3 and T6. The transistors T3-T6 form a NOR gate, so that node D goes to logic H only when both signals /WE and /WEd are at logic L. The transistor T7 turns on when node D is at logic L to charge the step-up capacitor C1 to the power source voltage Vdd. Therefore, when node D goes to logic H, the transistor T7 turns off, and the sum of the voltage of node D and the charged voltage of the step-up capacitor C1, (i.e., an electrical potential which is equal to or higher than the power source voltage Vdd) is supplied to the word line driver 16. In this manner, the electrical potential X of the word line WL is temporarily raised to a voltage level equal to or higher than Vdd after the write-in has been completed. Thus, the voltage of node B in the memory cell 10 is drastically raised to Vdd after the write-in has been completed.
In the above-described conventional device, the step-up circuit 24 must step-up the potential of the step-up lines having a very large capacitance, because the step-up signals are directly supplied to the positive power source terminal of the word line driver 16 to step-up the corresponding word line WL. Therefore, the scale of the step-up circuit 24 must be very large, and thus, there is an increase in the layout area and power consumption of the device.
Additionally, in the conventional device, the step-up pulse is generated on detection of the rising edge of the write enable signal /WE (i.e., at the end of writing). Therefore, there is a drawback in that the step-up operation is not performed when the write enable signal /WE is fixed in the state of logic L (i.e., when the address signals and input data vary in the write cycle).
Moreover, in the conventional device, the step-up of the word lines is performed after write-in is completed (i.e., after the write enable write enable signal /WE goes to logic H from logic L). Due to this, there is another drawback in that the precharge and equalizing operation of the pair of bit lines cannot be performed immediately after the write-in, so it takes a very long time to transfer from a write cycle to a read cycle.
To reduce the capacitance of the step-up lines, the device disclosed in Japanese Patent Laid-open Application Heisei 4-212788 (by this applicant) has been proposed. In this device, the word lines are divided into multiple blocks in the direction of the word lines, and the region where the memory cells are positioned is divided into blocks corresponding to the divided word lines. This forms the multiple memory cell array blocks used in the device, as shown in FIG. 21 of the Official Gazette. Also, the step-up circuits, which are shown in FIG. 5 of the Official Gazette, are positioned in each of the blocks, and the step-up operation is performed in every block by one of the step-up circuits based on the block selective signals.
However, in the device of Japanese Patent Laid-open Application Heisei 4-212788, as many step-up circuits (including step-up capacitors) are required as the number of blocks, so there is an increase in the layout area for the step-up circuits as a whole.
Further, Japanese Publication Application Showa 62-28516 and 62-28517 also discloses semiconductor memory devices in which the region for arranging the memory cells is divided into blocks. However, there is no disclosure with respect to the step-up operation.